The High Luminosity upgrade of the LHC (HL-LHC) is expected to take over in less than a decade. The HL-LHC will provide instantaneous luminosities five times larger than the LHC nominal value and data samples larger by one order of magnitude. In this high-luminosity environment, with more than 200 collisions happening at the same time in every beam crossing, maintaining the performance of vertex and track reconstruction, lepton identification, and flavor tagging will be extremely complicated. Several upgrades are planned to the ATLAS detector, the so called Phase-II upgrade, in order to successfully meet this challenge.
To use of information from the tracking as early as possible in the trigger selection is a central feature of the new TDAQ planned for Phase-II. The current plan, currently in the design stage, involves a hardware-based system (HTT) based on custom AM ASICs for pattern recognition and FPGAs for track reconstruction/fitting. Both Regional Tracking and Full Tracking are expected to be done in hardware with quasi offline quality for the later. The system is intended to be flexible enough to be adapted to run at L1 if needed. During this talk I will present the case for the HTT, the current planned components and how they will operate, and what we can expect in terms of performance.