CP3 Lunch -Simulation of Single Event Burnout in power MOSFET and designing an anti-latchup system for ASIC- Aurore Luu

by Dr Aurore Luu (CP3)

Wednesday 6 Apr 2011, 13:00 → 14:00 Europe/Brussels

E/3rd floor-E.349 - Seminar room (E.349) (Marc de Hemptinne (chemin du Cyclotron, 2, Louvain-la-Neuve))

Electronic devices embedded in spatial and aeronautic applications are exposed to a natural radiative environment. This environment can generate failures in the electronic systems and affect the application and the mission more or less seriously. To ensure the reliability of a device, we need to understand the mechanisms of these failures and we also need to test them in order to characterise their sensitivity to radiations. In this talk, 2 types of failures associated to 2 different devices will be discussed: the Single Event Burnout (SEB) in power MOSFET and the Single Event Latchup (SEL) in ASIC. After a brief introduction of the context, TCAD simulations of SEB will be presented; then, the designing of anti-latchup system for ASIC will be explained.